Integrated circuits are widely used for microprocessor, memory and logic devices in consumer, industrial and military electronics. As the integration density of integrated circuit devices continues to increase, it becomes increasingly difficult to make contacts to the devices, such as transistors, in the integrated circuit.
In particular, in integrated circuit fabrication, an increase in device integration density generally causes a reduction in the integrated circuit ground rules and a narrowing of process margins. Accordingly, it is desirable to form contacts which connect devices in the integrated circuit to one another, having minimum feature sizes. Moreover, even when a contact is formed using minimum feature size, it must also be ensured that the contact does not inadvertently contact unintended layers due to misalignment of an etch mask during formation of the contact. For example, in a memory device, a gate electrode may inadvertently contact a bit line electrode, a bit line electrode may inadvertently contact a storage electrode or a gate electrode may inadvertently contact a storage electrode. Any of these inadvertent contacts may render a memory device inoperable and will thereby lower the yield of the fabrication process.
In view of the above, various techniques have been developed for miniaturizing a contact while minimizing the risk of inadvertent contact to another layer as a result of misalignment of an etch mask or other factors. One such technique is self-aligned contact formation. Self-aligned contact formation may be used to form contacts of reduced sizes without the need for a separate mask.
Referring now to FIGS. 1-3, a fabrication method of a conventional semiconductor device using self-aligned contacts will be described. FIG. 1 is a top view of a conventional layout for manufacturing a semiconductor device having two contact pads. In particular, the layout of FIG. 1 may be used to manufacture a Dynamic Random Access Memory (DRAM) device. Reference numeral P1 indicates a first mask pattern which is used to manufacture field oxide regions in an inactive region of a semiconductor substrate. Reference numeral P2 indicates a second mask pattern which is used to form a gate electrode. Reference numeral P3 indicates a third mask pattern which is used to form a bit line pad. Reference numeral P4 indicates a fourth mask pattern which is used to form a storage pad. Reference numeral P5 indicates a fifth mask pattern which is used to connect a bit line pad to the bit line, and reference numeral P6 indicates a sixth mask pattern which forms a fourth contact hole to connect the storage pad to a storage electrode. Finally, reference numeral R1 indicates a contact region between the storage electrode and the source, and reference numeral R2 indicates a contact region between the bit line and the drain.
FIGS. 2A and 2B are cross-sectional views which illustrate a semiconductor device having a pair of contact pads taken along line II-II' of FIG. 1, during intermediate fabrication steps. As shown in FIG. 2A, a field oxide film 12 is formed in a semiconductor substrate to define inactive regions thereof, using the first mask pattern P1. A gate oxide film 14 is then formed on the semiconductor substrate 10. A polysilicon layer and an insulating film are deposited on the gate oxide film 14, and patterned, to thereby form a gate electrode 16 which is insulated by an insulating film 18. This patterning process is performed using mask pattern P2 of FIG. 1.
An oxide film is then deposited on the resultant structure, including on the gate electrode 16. The oxide film is anisoptropically etched to thereby form spacers 20 on the sidewalls of the gate electrode 16 and on the insulating film 18. Dopants are then implanted into the surface of the substrate to thereby form a source region 22 and a drain region 24. It will be understood that during the anisotropic etching described above for forming the spacer 20, a portion of the gate oxide film in the regions where the source and drains are to be formed, is also partially etched. This etching forms first and second contact holes 15 and 17, to expose a portion of the substrate where the source and drain regions are to be formed. The source region is formed at region R1 of FIG. 1, and the drain is formed at region R2 of FIG. 1.
Still referring to FIG. 2A, a doped polysilicon layer is formed on the resultant structure, including on self-aligned contact holes 15 and 17. The polysilicon layer is then etched using the third and fourth mask patterns P3 and P4 of FIG. 1, to thereby form a storage pad 26 which is electrically connected to the source 22 through the first contact hole 15, and a bit line pad 28 which is connected to the drain region 24 through the second contact hole 17.
Referring now to FIG. 2B, an insulating material such as borophosphorsilicate-glass (BPSG) is deposited and then reflowed at a high temperature to thereby form a planarized layer 30. The planarized layer 30 is anisotropically etched using the fifth mask pattern P5 of FIG. 1, to thereby form a third contact hole 32, also referred to as a bit line contact hole. A bit line 34 is then connected to the bit line pad 28 through the third contact hole 32. Another insulating layer is then formed on the substrate and a fourth contact hole, referred to as a storage electrode contact hole (not shown) is formed to connect the storage pad 26 to a storage electrode (also not shown). The storage electrode is then formed using the sixth mask pattern P6 of FIG. 1.
Still referring to FIGS. 2A and 2B, in order to separate the storage pad 26 and the bit line pad 28 from each other, a separation space between the pads is formed by etching the polysilicon layer, as described above. The space is then filled with insulating material such as the planarization layer 30. Unfortunately, as the integration density continues to increase and the separation between the storage pad and bit line pad continues to decrease, it becomes increasingly difficult to maintain the separation between the pads. This separation distance is denoted by L1 in FIG. 1.
Attempts have been made to maintain the separation between the pads notwithstanding their shrinking dimensions, by using lower wavelengths of light in the photolithography process. However, due to mask alignment tolerances, it still generally becomes necessary to maintain a minimum separation distance between the pads, thus precluding more dense integration.
Moreover, during fabrication of the pads, a conductive polysilicon bridge may form between the pads due to their small separation, thereby degrading the device yield and reliability. Finally, the pads are generally formed in an active region of a semiconductor device. The storage electrode contact holes and the bit line contact hole are also located within the active region as shown in P5 and P6 of FIG. 1. Since the distance L2 of FIG. 1 between the storage electrode contact holes or the distance L3 of FIG. 1 between a storage electrode contact hole and the bit line contact hole decrease as integration density increases, the process margins also decrease.
In view of the above, it has become exceedingly difficult to fabricate closely spaced pads of small dimensions while maintaining adequate pad separation, to produce functional and reliable devices with acceptable fabrication yields.